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1CY 7C26 5
CY7C265
8K x 8 Registered PROM
Features
* CMOS for optimum speed/power * High speed (commercial and military) -- 15 ns address set-up -- 12 ns clock to output * Low power -- 660 mW (commercial) -- 770 mW (military) * On-chip edge-triggered registers -- Ideal for pipelined microprogrammed systems * EPROM technology -- 100% programmable -- Reprogrammable (7C265W) * 5V 10% VCC, commercial and military * Capable of withstanding >2001V static discharge * Slim 28-pin, 300-mil plastic or hermetic DIP If the asynchronous enable (E) is being used, the outputs may be disabled at any time by switching the enable to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW. If the synchronous enable (ES) is being used, the outputs will go to the OFF or high-impedance state upon the next positive clock edge after the synchronous enable input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW, the subsequent positive clock edge will return the output to the active state. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C265 decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs. If the E/I pin is used for INIT (asynchronous), then the outputs are permanently enabled. The initialize function is useful during power-up and time-out sequences, and can facilitate implementation of other sophisticated functions such as a built-in "jump start" address. When activated, the initialize control input causes the contents of a user programmed 8193rd 8-bit word to be loaded into the on-chip register. Each bit is programmable and the initialize function can be used to load any desired combination of 1's and 0's into the register. In the unprogrammed state, activating INIT will generate a register clear (all outputs LOW). If all the bits of the initialize word are programmed to be a 1, activating INIT performs a register preset (all outputs HIGH). Applying a LOW to the INIT input causes an immediate load of the programmed initialize word into the pipeline register and onto the outputs. The INIT LOW disables clock and must return HIGH to enable clock independent of all other inputs, including the clock.
Functional Description
The CY7C265 is a 8192 x 8 registered PROM. It is organized as 8,192 words by 8 bits wide, and has a pipeline output register. In addition, the device features a programmable initialize byte that may be loaded into the pipeline register with the initialize signal. The programmable initialize byte is the 8,193rd byte in the PROM and its value is programmed at the time of use. Packaged in 28 pins, the PROM has 13 address signals (A0 through A12), 8 data out signals (O0 through O 7), E/I (enable or initialize), and CLOCK. CLOCK functions as a pipeline clock, loading the contents of the addressed memory location into the pipeline register on each rising edge. The data will appear on the outputs if they are enabled. One pin on the CY7C265 is programmed to perform either the enable or the initialize function.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 April 1988 - Revised April 1995
CY7C265
Logic Block Diagram Pin Configurations
DIP/Flatpack Top View
A12 A11 A10 A9 A8 A7 A6 A5 A5 A4 A3 A2 A1 A0 CLK PROGRAMMABLE MULTIPLEXER COLUMN ADDRESS O2 O1 ADDRESS DECODER 8-BIT EDGETRIGGERED REGISTER O4 O3 ROW ADDRESS PROGRAMMABLE ARRAY COLUMN MULTIPLEXER O5 O6 O7 A7 A6 A5 A4 A3 A2 GND CLK A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 7C265 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A8 A9 A10 A11 A12 E/ES,I GND GND O7 O6 O5 O4 O3 C265-3 O0
LCC/PLCC (Opaque Only) Top View
A4 A5 A6 A7 VCC A8 A9 4 3 2 1 28 27 26 25 24 23 22 21 20 19 12 13 14 15 16 17 18 O1 O2 GND O3 O4 O5 O6 C265-2 A10 A11 A12 E/ES,I GND GND O7
INIT/E/ES CLK
D C
O
A3 A2 GND CLK A1 A0 O0
5 6 7 8 9 10 11
C265-1
F
Selection Guides
7C265-15 Minimum Address Set-Up Time (ns) Maximum Clock to Output (ns) Maximum Operating Current (mA) Com'l Mil 15 12 120 140 7C265-25 25 15 120 140 7C265-40 40 20 100 7C265-50 50 25 80 120
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied.............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V DC Program Voltage .....................................................13.0V UV Exposure.................................................7258 Wsec/cm2
Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial[1] Military[2] Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC 5V 10% 5V 10% 5V 10%
Notes: 1. Contact a Cypress representative for industrial temperature range specifications. 2. TA is the "instant on" case temperature.
2
CY7C265
Electrical Characteristics Over the Operating Range[3]
7C265-15, 25 Parameter VOH VOL Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Com'l VCC = Min., IOL = 12.0 mA VCC = Min., IOL = 6.0 mA Mil VCC = Min., IOL = 8.0 mA VIH VIL IIX IOZ IOS[4] ICC VPP IPP VIHP VILP Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current VCC Operating Supply Current Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage 3.0 0.4 GND < VIN < VCC GND < VOUT < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Com'l Mil 12 -10 -40 2.0 0.8 +10 +40 90 120 140 13 50 3.0 0.4 12 13 50 3.0 0.4 12 -10 -40 2.0 0.8 +10 +40 90 100 -10 -40 2.0 0.8 +10 +40 90 80 120 13 50 V mA V V 0.4 0.4 V V A A mA mA 0.4 0.4 0.4 Min. 2.4 2.4 2.4 V 7C265-40 7C265-50 V
Max. Min. Max. Min. Max. Unit
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
Notes: 3. See the last page of this specification for Group A subgroup testing information. 4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 5. See Introduction to CMOS PROMs in this Data Book for general information on testing.
3
CY7C265
AC Test Loads and Waveforms
Test Load for - 15 through - 25 speeds
R1 500 (658 MIL) 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 333 (403 MIL) 5 pF INCLUDING JIG AND SCOPE R2 333 (403 MIL) R1 500 (658 MIL) 3.0V GND 5 ns 90% 10% 90% 10% 5 ns
C269-4
C269-5
(a) Normal Load
Equivalent to: OUTPUT THEVENIN EQUIVALENT RTH 200 250 MIL
(b) High Z Load
Test Load for - 40 through - 50 speeds
R1 250 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 167 5 pF INCLUDING JIG AND SCOPE R2 167 R1 250
C269-6
(c) Normal Load
Equivalent to: THEVENIN EQUIVALENT RTH 100 OUTPUT 2.0V
(d) High Z Load
Switching Characteristics Over the Operating Range[3, 5]
7C265-15 Parameter tAS tHA tCO tPWC tSES tHES tDI tRI tPWI tCOS tHZC tDOE tHZE Description Address Set-Up to Clock Address Hold from Clock Clock to Output Valid Clock Pulse Width ES Set-Up to Clock (Sync. Enable Only) ES Hold from Clock INIT to Output Valid INIT Recovery to Clock INIT Pulse Width Output Valid from Clock (Sync. Mode) Output Inactive from Clock (Sync. Mode) Output Valid from E LOW (Async. Mode) Output Inactive from E HIGH (Async. Mode) 12 12 12 12 12 12 12 12 5 15 15 15 15 15 15 15 Min. 15 0 12 15 15 5 18 20 25 20 20 20 20 Max. 7C265-25 Min. 25 0 15 15 15 5 25 25 35 25 25 25 25 Max. 7C265-40 Min. 40 0 20 20 15 5 35 Max. 7C265-50 Min. 50 0 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
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CY7C265
Switching Waveform
ADDRESS tAS SYNCHRONOUS ENABLE (PROGRAMMABLE) tSES CLOCK tPWC OUTPUT tDI tPWI ASYNCHRONOUS INIT (PROGRAMMABLE) tRI ASYNCHRONOUS ENABLE
C265-7
tAH
tHES
tCOS
tCO
VALID DATA tHZC tHZE tDOE
Erasure Characteristics Bit Map Data
Wavelengths of light less than 4000 angstroms begin to erase the 7C265 in the windowed package. For this reason, an opaque label should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time. The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity * exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure time would be approximately 45 minutes. The 7C265 needs to be within one inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage. Programmer Address (Hex.) Decimal 0 . . 8191 8192 8193 Control Byte 00 01 02 Asynchronous output enable (default condition) Synchronous output enable Asynchronous initialize Hex 0 . . 1FFF 2000 2001 RAM Data Contents Data . . Data INIT Byte Control Byte
Programming Modes
The 7C265 offers a limited selection of programmed architectures. Programming these features should be done with a single 10-ms-wide pulse in place of the intelligent algorithm, mainly because these features are verified operationally, not with the VFY pin. Architecture programming is implemented by applying the supervoltage to two additional pins during programming. In programming the 7C265 architecture, VPP is applied to pins 3, 9, and 22. The choice of a particular mode depends on the states of the other pins during programming, so it is important that the condition of the other pins be met as set forth in the mode table. The considerations that apply with respect to power-up and power-down during intelligent programming also apply during architecture programming. Once the supervoltages have been established and the correct logic states exist on the other device pins, programming may begin. Programming is accomplished by pulling PGM from HIGH to LOW and then back to HIGH with a pulse width equal to 10 ms.
5
CY7C265
Table 1. Mode Selection Pin Function Read or Output Disable Mode Other Asynchronous Enable Read Synchronous Enable Read Asynchronous Initialization Read Program Memory Program Verify Program Inhibit Program Synchronous Enable Program Initialize Program Initial Byte A12 A12 A12 A12 A12 A12 A12 A12 VIHP VILP A12 A11 A11 A11 A11 A11 A11 A11 A11 VIHP VIHP VILP A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A6 A6 A6 A6 A6 A6 A6 A6 VIHP VIHP VIHP Pin Function Read or Output Disable Mode Other Asynchronous Enable Read Synchronous Enable Read Asynchronous Initialization Read Program Memory Program Verify Program Inhibit Program Synchronous Enable Program Initialize Program Initial Byte A1 A1 A1 A1 A1 A1 A1 A1 VPP VPP VPP A0 A0 A0 A0 A0 A0 A0 A0 VILP VILP VIHP GND PGM GND GND GND VILP VIHP VIHP VILP VILP VILP CLK CLK VIL VIL/VIH VIL VILP VILP VILP VILP VILP VILP GND VFY GND GND GND VIHP VILP VIHP VIHP VIHP VIHP E, I VPP VIL VIL VIL VPP VPP VPP VPP VPP VPP O7 - O0 D7 - D0 O7 - O0 O7 - O0 O7 - O0 D7 - D0 O7 - O0 High Z D7 - D0 D7 - D0 D7 - D0 A5 A5 A5 A5 A5 A5 A5 A5 VPP VPP VPP A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A2 A2 A2 A2 A2 A2 A2 A2 VIHP VILP VILP
DIP/Flatpack
A7 A6 A5 A4 A3 A2 PGM CLK A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A8 A9 A10 A11 A12 VPP NA VFY D7 D6 D5 D4 D3 C265-8
LCC/PLCC (Opaque Only)
A3 A2 PGM CLK A1 A0 D0
4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 1314151617 18
A10 A11 A12 VPP NA VFY D7
C265-9
Figure 1. Programming Pinout
Programming Information
Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed
programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative.
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CY7C265
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.6 1.4 1.2 ICC 1.0 20 0.8 0.6 4.0 0.9 TA =25C f=MAX. 4.5 5.0 5.5 6.0 10 0.8 -55 25 125 0 0.0 1.0 2.0 3.0 4.0 1.0 1.2 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 60 50 1.1 40 ICC 30 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE
SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 125 1.2 1.0 0.8 0.6 -55 100 75 50 25 25 125 0 0.0 175 150
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 35 30 25 20 15 10
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC =5.0V TA =25C 1.0 2.0 3.0 4.0
5 0 0 200 400
VCC =4.5V TA =25C 600 800 1000
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
CAPACITANCE (pF)
NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0 25 50 75 100 CLOCK PERIOD (ns) VCC =5.5V TA =25C
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CY7C265
Ordering Information[6]
Speed (ns) 15 ICC (mA) 120 Ordering Code CY7C265-15JC CY7C265-15PC CY7C265-15WC 140 CY7C265-15DMB CY7C265-15LMB CY7C265-15QMB CY7C265-15WMB 25 120 CY7C265-25JC CY7C265-25PC CY7C265-25WC 140 CY7C265-25DMB CY7C265-25LMB CY7C265-25QMB CY7C265-25WMB 40 100 CY7C265-40JC CY7C265-40PC CY7C265-40WC 50 80 CY7C265-50JC CY7C265-50PC CY7C265-50WC 120 CY7C265-50DMB CY7C265-50LMB CY7C265-50QMB CY7C265-50WMB Package Name J64 P21 W22 D22 L64 Q64 W22 J64 P21 W22 D22 L64 Q64 W22 J64 P21 W22 J64 P21 W22 D22 L64 Q64 W22 Package Type 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead (300-Mil) Windowed CerDIP Military Commercial Commercial Military Commercial Military Operating Range Commercial
Note: 6. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability.
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tAS tHA tCO tPW tSES tHES tCOS
Switching Characteristics
Parameter Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Document #: 38-00084-E
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CY7C265
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
28-Lead Plastic Leaded Chip Carrier J64
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
28-Pin Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C-4
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CY7C265
Package Diagrams (continued)
28-Lead (300-Mil) Molded DIP P21
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835 D- Config. A 15
(c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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